Electronic Design

Talking About Mentor’s Tessent Streaming Scan Network and how it Addresses Next-Gen IC Test

Addressing the complexity of modern ICs and their multiple cores is a challenge to the testing community. Mentor's Tessent Streaming Scan Network can ease this problem. We talk to the company's Geir ...
EDN

Mentor Graphics reveals new strategy to unify silicon test and yield analysis

Winchester, UK – Mentor Graphics Corporation has outlined its new strategy to help customers address the growing test challenges they face in moving to smaller process nodes and more complex, ...
Semiconductor Engineering

Success Stories For Packetized Scan Data

Some new design-for-test (DFT) technologies are difficult, expensive, or risky to implement but offer significant benefits. Other technologies are easy to implement but offer minor improvements. The ...
Design-Reuse

Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight

The world of System-on-Chips (SoCs) is evolving - with the advancement of generative AI, the increasing demand for high-performance compute, and the innovative shift towards multi-chiplet ...
Electronic Design

Mentor debuts Tessent Connect and Tessent Safety at ITC

Mentor, a Siemens business, has introduced Tessent Connect, a design-for-test (DFT) automation methodology that delivers intent-driven hierarchical test implementation that helps IC design teams ...
EDN

Test solutions to confront silent data corruption in ICs

While semiconductor design engineers become more aware of silent data corruption (SDC) or silent data errors (SDE) caused by aging, environmental factors, and other issues, embedded test solutions are ...